Shallow trench isolation (STI) is a standard process used in nanofabrication to isolate the active areas of semiconductor devices. An STI process generally consists of digging trenches in the silicon wafers and filling them with a dielectric oxide material. A typical STI process includes a chemical mechanical polishing (CMP) step to planarize the dielectric oxide material after it has been deposited into the shallow trenches. Standard CMP processes generally use a silica-based oxide slurry to polish the STI layers.
Shallow trench isolation CMP using conventional, silica-based oxide slurries has a number of problems such as variation of pattern density across the die, non-uniform polishing rate within the wafer, and insufficient selectivity of oxide to nitride. Furthermore, current silica-based oxide slurries are not capable of meeting planarity requirements of STI modules for the sub-65 nm technology node. Silica-based slurries may leave oxide in some areas of the wafer while polishing nitride in other areas of the wafer, thereby causing problems for subsequent processing steps due to poor planarity on the surface of the polished wafer.
Ceria-abrasive based slurries are another option because they provide a unique across wafer uniformity advantage. These slurries do not have significant nitride polish rates, thereby allowing the polishing process to be stopped when the nitride layer is exposed without significant polishing of the nitride layer occurring. This results in excellent across-wafer uniformity. Ceria based slurries, however, entail a higher cost and have a higher incidence of defects.